59 lines
1.4 KiB
Verilog
59 lines
1.4 KiB
Verilog
`timescale 1ns/1ps
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module sigmadelta_input #(
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parameter integer R_OHM = 3300,
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parameter integer C_PF = 220
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)(
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input wire clk_15,
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input wire resetn,
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input wire adc_a,
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input wire adc_b,
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output wire adc_o,
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output wire signed [15:0] signal_q15,
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output wire signal_valid
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);
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`include "rc_alpha_q15.vh"
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wire sd_signal;
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wire signed [15:0] raw_sample_q15;
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wire signed [15:0] lpf_sample_q15;
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sigmadelta_sampler sd_sampler(
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.clk(clk_15),
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.a(adc_a), .b(adc_b),
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.o(sd_signal)
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);
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assign adc_o = sd_signal;
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localparam integer alpha_q15_int = alpha_q15_from_rc(R_OHM, C_PF, 15000000);
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localparam signed [15:0] alpha_q15 = alpha_q15_int[15:0];
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localparam signed [15:0] alpha_q15_top = alpha_q15 & 16'hff00;
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sigmadelta_rcmodel_q15 #(
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.alpha_q15(alpha_q15_top)
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) rc_model (
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.clk(clk_15), .resetn(resetn),
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.sd_sample(sd_signal),
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.sample_q15(raw_sample_q15)
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);
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lpf_iir_q15_k #(
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.K(10)
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) lpf (
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.clk(clk_15), .rst_n(resetn),
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.x_q15(raw_sample_q15),
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.y_q15(lpf_sample_q15)
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);
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decimate_by_r_q15 #(
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.R(375), // 15MHz/375 = 40KHz
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.CNT_W(10)
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) decimate (
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.clk(clk_15), .rst_n(resetn),
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.in_valid(1'b1), .in_q15(lpf_sample_q15),
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.out_valid(signal_valid), .out_q15(signal_q15)
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);
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endmodule
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