Got rid of ftw_we and tested on hw with freq sweep

rtl/core/nco_q15.v

@@ -23,7 +23,6 @@ module nco_q15 #
 
   // Frequency control
   input  wire [31:0] ftw_in,      // Frequency Tuning Word (FTW)
-  input  wire        ftw_we,      // write-enable strobe (1 clk pulse)
 
   // Outputs (valid on clk_en rising pulse, i.e., at FS_HZ)
   output reg  signed [15:0] sin_q15, // signed Q1.15 sine
@@ -48,7 +47,7 @@ module nco_q15 #
   // If you prefer, replace 16 with $clog2(DIV) on a tool that supports it well.
   reg [15:0] tick_cnt;
 
-  always @(posedge clk or negedge rst_n) begin
+  always @(posedge clk) begin
     if (!rst_n) begin
       tick_cnt <= 16'd0;
       clk_en   <= 1'b0;
@@ -65,12 +64,11 @@ module nco_q15 #
 
   // ==========================================================
   // Frequency control register
-  // - You present ftw_in and pulse ftw_we (1 clk) to update.
+  // - You present ftw_in
   // ==========================================================
   reg [31:0] ftw;
-  always @(posedge clk or negedge rst_n) begin
-    if (!rst_n) ftw <= ftw_from_hz(1000, PHASE_BITS, FS_HZ); // Start at 1khz
-    else if (ftw_we) ftw <= ftw_in;
+  always @(posedge clk) begin
+    ftw <= ftw_in;
   end
 
   // ==========================================================
@@ -82,7 +80,7 @@ module nco_q15 #
   reg  [PHASE_BITS-1:0] phase_sin, phase_cos;
   wire [PHASE_BITS-1:0] phase_cos_plus90 = phase_sin + ({{(PHASE_BITS-2){1'b0}}, 2'b01} << (PHASE_BITS-2)); // +90°
 
-  always @(posedge clk or negedge rst_n) begin
+  always @(posedge clk) begin
     if (!rst_n) begin
       phase_sin <= {PHASE_BITS{1'b0}};
       phase_cos <= {PHASE_BITS{1'b0}};
@@ -132,11 +130,11 @@ module nco_q15 #
   // ==========================================================
   // Output registers (update on clk_en)
   // ==========================================================
-  always @(posedge clk or negedge rst_n) begin
+  always @(posedge clk) begin
     if (!rst_n) begin
       sin_q15 <= 16'sd0;
       cos_q15 <= 16'sd0;
-    end else if (clk_en) begin
+    end else begin
       sin_q15 <= sin_q15_next;
       cos_q15 <= cos_q15_next;
     end

rtl/toplevel/top_generic.v

@@ -15,16 +15,38 @@ module top_generic(
     assign led_green = 1'b0;
     assign led_red = 1'b0;
 
+
+    reg [11:0] count;
+    localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz
+    reg [16:0] div_counter = 0;               // enough bits for 100k (2^17=131072)
+    always @(posedge aclk) begin
+        if (!aresetn) begin
+            div_counter <= 0;
+            count <= 0;
+        end else begin
+            if (div_counter == DIV_MAX) begin
+                div_counter <= 0;
+                if (count == 12'd3999)
+                    count <= 0;               // wrap at 4000
+                else
+                    count <= count + 1'b1;    // increment every 1 ms
+            end else begin
+                div_counter <= div_counter + 1'b1;
+            end
+        end
+    end
+
+
     wire [15:0] sin_q15;
     wire clk_en;
     nco_q15 #(
         .CLK_HZ(100_000_000),
-        .PHASE_BITS(16)
+        .PHASE_BITS(16),
+        .FS_HZ(40_000)
     ) nco (
         .clk    (aclk),
         .rst_n  (aresetn),
-        .ftw_in (32'h0),
-        .ftw_we (1'b0),
+        .ftw_in (ftw_from_hz(count, 16, 40_000)),
         .sin_q15(sin_q15),
         .cos_q15(),
         .clk_en (clk_en)
@@ -37,9 +59,9 @@ module top_generic(
     wire [5:0] dac_code_next = biased[15:10];     // 0..63 (MSB=bit5)
     // Register it at the sample rate (clk_en)
     reg [5:0] dac_code;
-    always @(posedge aclk or negedge aresetn) begin
+    always @(posedge aclk) begin
         if (!aresetn) dac_code <= 6'd0;
-        else if (clk_en) dac_code <= dac_code_next;
+        else dac_code <= dac_code_next;
     end
     assign r2r = dac_code;
 endmodule

sim/tb/tb_nco_q15.v

@@ -21,7 +21,6 @@ module tb_nco_q15();
 
 
     reg [31:0] ftw_in;
-    reg ftw_we;
     wire [15:0] sin_q15;
     wire [15:0] cos_q15;
     wire out_en;
@@ -30,7 +29,6 @@ module tb_nco_q15();
         .clk    (clk),
         .rst_n  (resetn),
         .ftw_in (ftw_in),
-        .ftw_we (ftw_we),
         .sin_q15(sin_q15),
         .cos_q15(cos_q15),
         .clk_en (out_en)
@@ -38,13 +36,10 @@ module tb_nco_q15();
 
     initial begin
         ftw_in = 32'h0;
-        ftw_we = 1'b0;
         #100
-        @(posedge clk);
         ftw_in = ftw_from_hz(1000, 16, 40000);
-        ftw_we = 1'b1;
-        @(posedge clk);
-        ftw_we = 1'b0;
+        #2_500_000
+        ftw_in = ftw_from_hz(2000, 16, 40000);
     end;
 
 endmodule