45 lines
868 B
Verilog
45 lines
868 B
Verilog
`timescale 1ns/1ps
|
|
|
|
module tb_nco_q15();
|
|
`include "core/nco_q15_funcs.vh"
|
|
|
|
// Clock and reset generation
|
|
reg clk;
|
|
reg resetn;
|
|
initial clk <= 1'b0;
|
|
initial resetn <= 1'b0;
|
|
always #4.17 clk <= !clk;
|
|
initial #40 resetn <= 1'b1;
|
|
|
|
// Default run
|
|
initial begin
|
|
$dumpfile("out.vcd");
|
|
$dumpvars;
|
|
#5_000_000
|
|
$finish;
|
|
end;
|
|
|
|
|
|
reg [31:0] ftw_in;
|
|
wire [15:0] sin_q15;
|
|
wire [15:0] cos_q15;
|
|
wire out_en;
|
|
|
|
nco_q15 #(.PHASE_BITS(16)) nco (
|
|
.clk (clk),
|
|
.rst_n (resetn),
|
|
.ftw_in (ftw_in),
|
|
.sin_q15(sin_q15),
|
|
.cos_q15(cos_q15),
|
|
.clk_en (out_en)
|
|
);
|
|
|
|
initial begin
|
|
ftw_in = 32'h0;
|
|
#100
|
|
ftw_in = ftw_from_hz(1000, 16, 40000);
|
|
#2_500_000
|
|
ftw_in = ftw_from_hz(2000, 16, 40000);
|
|
end;
|
|
|
|
endmodule |