Added xsim postsimulation

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/zynq7000/RTL/heartbeat.vhd

@@ -4,7 +4,7 @@ use ieee.numeric_std.all;
 entity heartbeat is
     generic (
         Fin  : integer := 100000000;
-        Fout : integer := 8
+        Fout : integer := 10000000
     );
     port (
         ACLK    : in std_logic;

examples/zynq7000/RTL/toplevel.vhd

@@ -78,7 +78,7 @@ architecture structural of toplevel is
     component heartbeat is
         generic (
             Fin  : integer := 100000000;
-            Fout : integer := 8
+            Fout : integer := 10000000
         );
         port (
             ACLK    : in std_logic;
@@ -93,10 +93,12 @@ architecture structural of toplevel is
     signal FCLK_RESET0_N : std_logic;
     signal ARESETN : std_logic_vector(0 downto 0);
 begin
-    heartbeat_i : component heartbeat generic map(
-        100000000,
-        10
-        ) port map(
+    heartbeat_i : component heartbeat 
+    -- generic map(
+    --     100000000,
+    --     10
+    -- ) 
+    port map(
         ACLK    => FCLK_CLK0,
         ARESETN => ARESETN(0),
         LED     => LED

examples/zynq7000/SIM/tb_heartbeat.vhd

@@ -9,10 +9,10 @@ architecture behavioural of tb_heartbeat is
     -- COMPONENTS
     -- ----------
     component heartbeat is
-        generic (
-            Fin  : integer := 100000000;
-            Fout : integer := 8
-        );
+        -- generic (
+            -- Fin  : integer := 100000000;
+            -- Fout : integer := 8
+        -- );
         port (
             ACLK    : in std_logic;
             ARESETN : in std_logic;
@@ -25,10 +25,12 @@ architecture behavioural of tb_heartbeat is
     signal LED : std_logic_vector(1 downto 0) := "00";
     signal ARESETN : std_logic := '0';
 begin
-    c_heartbeat : component heartbeat generic map(
-        50000000,
-        5000000
-        ) port map(
+    c_heartbeat : component heartbeat 
+    -- generic map(
+    --     50000000,
+    --     5000000
+    -- ) 
+    port map(
         ACLK    => ACLK,
         ARESETN => ARESETN,
         LED     => LED

examples/zynq7000/project.cfg

@@ -39,7 +39,8 @@ package             = clg400
 speedgrade          = -2
 toplevel            = toplevel
 # Created netlist toplevel
-netlist_top         = toplevel.heartbeat_i
+netlist_top         = toplevel.heartbeat_i heartbeat
+# toplevel and name to give to exported netlist
 synth_opts          = -flatten_hierarchy none -keep_equivalent_registers
 #opt_opts           =
 #place_opts         =
@@ -70,4 +71,23 @@ files_vhdl          = RTL/heartbeat.vhd
 #files_verilog      =
 #files_sysverilog   =
 #files_xci          = 
+# ######################################
+
+# ######################################
+# Post synthesis simulation (synth must have ran first)
+[target.psim]
+toolchain           = xsim
+
+# Toolchain settings
+toplevel            = tb_heartbeat
+vcdlevels           = 20
+runtime             = all
+xelab_opts          = -maxdelay -transport_int_delays -L simprims_ver
+
+# Fileset
+files_vhdl          = SIM/tb_heartbeat.vhd
+files_verilog       = OUT/synth/impl_netlist.v
+#files_sysverilog   =
+#files_xci          = 
+files_other         = OUT/synth/impl_netlist.sdf
 # ######################################