Added basic zynq setup

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/spartan6/README.md

@@ -1,5 +1,6 @@
 # Spartan 6 example
 
+Create IP files: `remotesyn -l ip total`<br>
 Run full toolchain: `remotesyn -l all total`<br>
 Run simulation: `remotesyn -l sim presim_total`<br>
 Run post-simulation (after synthesis and implementation): `remotesyn -l sim postsim_total`<br>

examples/spartan6/project.cfg

@@ -1,36 +1,44 @@
 # PROJECT SETTINGS
 # ----------------
 [server]
-hostname = localhost
-port = 8080
-privkey = keys/id_rsa
-pubkey = keys/id_rsa.pub
+hostname            = localhost
+port                = 8080
+privkey             = keys/id_rsa
+pubkey              = keys/id_rsa.pub
 
 [project]
 # Toolchain selection. choose between [ISE, VIVADO]
-toolchain = ISE
-out_dir = OUT
+toolchain           = ISE
+out_dir             = OUT
 
 [target]
-family = spartan6
-device = xc6slx9
-package = tqg144
-speedgrade = -2
+family              = spartan6
+device              = xc6slx9
+package             = tqg144
+speedgrade          = -2
 
 # HARDWARE TARGETS
 # ----------------
 [total]
-src_vhdl = RTL/toplevel.vhd
-src_verilog = 
-src_sysverilog = 
-src_constraints = CON/toplevel.ucf
-src_ip = 
-toplevel = toplevel
-extra_options = xst -glob_opt max_delay -opt_mode speed
-                netgen -ism
-                map -ol high -xe n
-                par -ol high -xe n
-                trce -v 3 -s 2 -n 3 -fastpaths
+src_vhdl            = RTL/toplevel.vhd
+src_verilog         = 
+src_sysverilog      = 
+src_constraints     = CON/toplevel.ucf
+src_ip              = blk_mem
+toplevel            = toplevel
+extra_options       = xst -glob_opt max_delay -opt_mode speed
+                      netgen -ism
+                      map -ol high -xe n
+                      par -ol high -xe n
+                      trce -v 3 -s 2 -n 3 -fastpaths
+# Currently supported for ISE
+# - xst -> settings added to the xst command
+# - netgen -> settings added to the netgen command
+# - ngd -> settings added to the ngd command
+# - map -> settigs added to the map command
+# - par -> settings added to the par command
+# - bitgen -> settings added to the bitgen command
+# - trce -> settings added to the trce command
 
 # SIMULATION TARGETS
 # ------------------
@@ -53,6 +61,18 @@ src_ip              =
 src_sdf             = OUT/total/total.map.sdf
 toplevel            = tb_toplevel
 runtime             = all
+# Delay type: [min typ max]
 delay               = max
 sdfroot             = /tb_toplevel/c_toplevel
-levels              = 10
+levels              = 10
+
+# IP BLOCKS 
+# ---------
+[ip_blk_mem]
+ip_blk_mem          = xilinx.com:ip:blk_mem_gen:7.3
+component_name      = blk_mem
+interface_type      = Native
+port_a_clock        = 100
+read_width_a        = 32
+write_width_a       = 32
+write_depth_a       = 256