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New project structure

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Rewrite of all functions

Signed-off-by: Jojojoppe <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-03 21:52:29 +02:00
parent cbcea361bb
commit 162aaf47a0
31 changed files with 209 additions and 2111 deletions
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2
examples/spartan6/.gitignore vendored
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OUT
.build

41
examples/spartan6/CON/toplevel.ucf
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NET "ACLK" LOC = P126;
NET "ACLK" TNM_NET = "SYS_CLK_PIN";
TIMESPEC TS_SYS_CLK_PIN = PERIOD "SYS_CLK_PIN" 10 ns HIGH 50 %;
NET "LED[0]" LOC = P119;
NET "LED[0]" IOSTANDARD = LVCMOS33;
NET "LED[0]" DRIVE = 8;
NET "LED[1]" LOC = P118;
NET "LED[1]" IOSTANDARD = LVCMOS33;
NET "LED[1]" DRIVE = 8;
NET "LED[2]" LOC = P117;
NET "LED[2]" IOSTANDARD = LVCMOS33;
NET "LED[2]" DRIVE = 8;
NET "LED[3]" LOC = P116;
NET "LED[3]" IOSTANDARD = LVCMOS33;
NET "LED[3]" DRIVE = 8;
NET "LED[4]" LOC = P115;
NET "LED[4]" IOSTANDARD = LVCMOS33;
NET "LED[4]" DRIVE = 8;
NET "LED[5]" LOC = P114;
NET "LED[5]" IOSTANDARD = LVCMOS33;
NET "LED[5]" DRIVE = 8;
NET "LED[6]" LOC = P112;
NET "LED[6]" IOSTANDARD = LVCMOS33;
NET "LED[6]" DRIVE = 8;
NET "LED[7]" LOC = P111;
NET "LED[7]" IOSTANDARD = LVCMOS33;
NET "LED[7]" DRIVE = 8;
NET "SW[0]" LOC = P124;
NET "SW[0]" IOSTANDARD = LVCMOS33;
NET "SW[0]" PULLUP;
NET "SW[1]" LOC = P123;
NET "SW[1]" IOSTANDARD = LVCMOS33;
NET "SW[1]" PULLUP;
NET "SW[2]" LOC = P121;
NET "SW[2]" IOSTANDARD = LVCMOS33;
NET "SW[2]" PULLUP;
NET "SW[3]" LOC = P120;
NET "SW[3]" IOSTANDARD = LVCMOS33;
NET "SW[3]" PULLUP;

6
examples/spartan6/README.md
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# Spartan 6 example
Create IP files: `remotesyn -l ip total`<br>
Run full toolchain: `remotesyn -l all total`<br>
Run simulation: `remotesyn -l sim presim_total`<br>
Run post-simulation (after synthesis and implementation): `remotesyn -l sim postsim_total`<br>

28
examples/spartan6/RTL/toplevel.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity toplevel is
port (
ACLK : in std_logic;
LED : out std_logic_vector(7 downto 0);
SW : in std_logic_vector(3 downto 0)
);
end toplevel;
architecture structural of toplevel is
signal ARESETN : std_logic;
begin
ARESETN <= SW(3);
process(ACLK, ARESETN)
begin
if ARESETN='0' then
LED <= "11111111";
elsif rising_edge(ACLK) then
LED <= SW & SW;
end if;
end process;
end architecture;

49
examples/spartan6/SIM/tb_toplevel.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_toplevel is
end entity;
architecture behavioural of tb_toplevel is
-- COMPONENTS
-- ----------
component toplevel is
port (
ACLK : in std_logic;
LED : out std_logic_vector(7 downto 0);
SW : in std_logic_vector(3 downto 0)
);
end component;
-- SIGNALS
-- -------
signal ACLK : std_logic := '0';
signal LED : std_logic_vector(7 downto 0) := "00000000";
signal SW : std_logic_vector(3 downto 0) := "0111";
begin
c_toplevel : component toplevel port map(
ACLK, LED, SW
);
ACLK <= not ACLK after 10 ns;
SW(3) <= '1' after 150 ns;
process
begin
wait until SW(3)='1';
SW(2 downto 0) <= "101";
wait for 75 ns;
SW(2 downto 0) <= "010";
wait for 19 ns;
SW(2 downto 0) <= "111";
wait for 100 ns;
report "END OF SIMULATION" severity failure;
end process;
end architecture;

78
examples/spartan6/project.cfg
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# PROJECT SETTINGS
# ----------------
[server]
hostname = localhost
port = 8080
privkey = keys/id_rsa
pubkey = keys/id_rsa.pub
[project]
# Toolchain selection. choose between [ISE, VIVADO]
toolchain = ISE
out_dir = OUT
[target]
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
# HARDWARE TARGETS
# ----------------
[total]
src_vhdl = RTL/toplevel.vhd
src_verilog =
src_sysverilog =
src_constraints = CON/toplevel.ucf
src_ip = blk_mem
toplevel = toplevel
extra_options = xst -glob_opt max_delay -opt_mode speed
netgen -ism
map -ol high -xe n
par -ol high -xe n
trce -v 3 -s 2 -n 3 -fastpaths
# Currently supported for ISE
# - xst -> settings added to the xst command
# - netgen -> settings added to the netgen command
# - ngd -> settings added to the ngd command
# - map -> settigs added to the map command
# - par -> settings added to the par command
# - bitgen -> settings added to the bitgen command
# - trce -> settings added to the trce command
# SIMULATION TARGETS
# ------------------
[presim_total]
simtype = presim
src_vhdl = RTL/toplevel.vhd
SIM/tb_toplevel.vhd
src_verilog =
src_sysverilog =
toplevel = tb_toplevel
runtime = all
levels = 10
[postsim_total]
simtype = postsim
src_vhdl = SIM/tb_toplevel.vhd
src_verilog = OUT/total/total.map.v
src_sysverilog =
src_ip =
src_sdf = OUT/total/total.map.sdf
toplevel = tb_toplevel
runtime = all
# Delay type: [min typ max]
delay = max
sdfroot = /tb_toplevel/c_toplevel
levels = 10
# IP BLOCKS
# ---------
[ip_blk_mem]
ip_blk_mem = xilinx.com:ip:blk_mem_gen:7.3
component_name = blk_mem
interface_type = Native
port_a_clock = 100
read_width_a = 32
write_width_a = 32
write_depth_a = 256