107 lines
2.3 KiB
Verilog
107 lines
2.3 KiB
Verilog
`timescale 1ns/1ps
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module tb_svf();
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reg clk;
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reg resetn;
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initial clk <= 1'b0;
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initial resetn <= 1'b0;
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always #33.33 clk <= !clk;
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initial #40 resetn <= 1'b1;
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wire [7:0] led_out;
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jtag_byte_sink #(
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.SVF_FILE("sim/other/test.svf"),
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.TCK_HALF_PERIOD_NS(500)
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) dut (
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.i_clk(clk),
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.i_rst(!resetn),
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.o_led(led_out)
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);
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initial begin
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$dumpfile("out.vcd");
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$dumpvars;
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#200_000;
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$finish;
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end
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endmodule
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module jtag_byte_sink #(
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parameter [8*256-1:0] SVF_FILE = "",
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parameter integer TCK_HALF_PERIOD_NS = 50
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)(
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input wire i_clk,
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input wire i_rst,
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output reg [7:0] o_led
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);
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initial o_led <= 0;
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// JTAG interface wires
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wire jtag_tck;
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wire jtag_tdi;
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wire jtag_drck;
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wire jtag_capture;
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wire jtag_shift;
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wire jtag_update;
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wire jtag_runtest;
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wire jtag_reset;
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wire jtag_sel;
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reg [41:0] jtag_q;
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reg [41:0] jtag_data;
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wire jtag_async_reset;
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jtag_if #(
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.chain(1),
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.SVF_FILE(SVF_FILE),
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.TCK_HALF_PERIOD_NS(TCK_HALF_PERIOD_NS),
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.USER_IR_OPCODE(32'h0000_0002)
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) jtag (
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.i_tdo(jtag_q[0]),
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.o_tck(jtag_tck),
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.o_tdi(jtag_tdi),
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.o_drck(jtag_drck),
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.o_capture(jtag_capture),
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.o_shift(jtag_shift),
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.o_update(jtag_update),
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.o_runtest(jtag_runtest),
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.o_reset(jtag_reset),
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.o_sel(jtag_sel)
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);
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assign jtag_async_reset = jtag_reset || i_rst;
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always @(posedge jtag_drck or posedge jtag_async_reset) begin
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if (jtag_async_reset) begin
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jtag_q <= 0;
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end else if (jtag_sel && jtag_capture) begin
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jtag_q <= jtag_data;
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end else if (jtag_sel && jtag_shift) begin
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jtag_q <= {jtag_tdi, jtag_q[41:1]};
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end
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end
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always @(posedge jtag_update or posedge jtag_async_reset) begin
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if (jtag_async_reset) begin
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jtag_data <= 0;
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end else if (jtag_sel) begin
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jtag_data <= jtag_q;
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end
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end
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wire [41:0] j_data;
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wire j_data_update;
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cdc_strobed #(42) j_data_cdc (
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.i_clk_a(i_clk),
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.i_clk_b(i_clk),
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.i_data(jtag_data),
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.i_strobe(jtag_update),
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.o_data(j_data),
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.o_strobe(j_data_update)
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);
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endmodule
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