`timescale 1ns/1ps

module tb_svf();
    reg clk;
    reg resetn;
    initial clk <= 1'b0;
    initial resetn <= 1'b0;
    always #33.33 clk <= !clk;
    initial #40 resetn <= 1'b1;

    wire [7:0] led_out;

    jtag_byte_sink #(
        .SVF_FILE("sim/other/test.svf"),
        .TCK_HALF_PERIOD_NS(500)
    ) dut (
        .i_clk(clk),
        .i_rst(!resetn),
        .o_led(led_out)
    );

    initial begin
        $dumpfile("out.vcd");
        $dumpvars;
        #200_000;
        $finish;
    end
endmodule

module jtag_byte_sink #(
    parameter [8*256-1:0] SVF_FILE = "",
    parameter integer TCK_HALF_PERIOD_NS = 50
)(
    input wire i_clk,
    input wire i_rst,
    output reg [7:0] o_led
);

    initial o_led <= 0;

    // JTAG interface wires
    wire jtag_tck;
    wire jtag_tdi;
    wire jtag_drck;
    wire jtag_capture;
    wire jtag_shift;
    wire jtag_update;
    wire jtag_runtest;
    wire jtag_reset;
    wire jtag_sel;

    reg [41:0] jtag_q;
    reg [41:0] jtag_data;
    wire jtag_async_reset;

    jtag_if #(
        .chain(1),
        .SVF_FILE(SVF_FILE),
        .TCK_HALF_PERIOD_NS(TCK_HALF_PERIOD_NS),
        .USER_IR_OPCODE(32'h0000_0002)
    ) jtag (
        .i_tdo(jtag_q[0]),
        .o_tck(jtag_tck),
        .o_tdi(jtag_tdi),
        .o_drck(jtag_drck),
        .o_capture(jtag_capture),
        .o_shift(jtag_shift),
        .o_update(jtag_update),
        .o_runtest(jtag_runtest),
        .o_reset(jtag_reset),
        .o_sel(jtag_sel)
    );


    assign jtag_async_reset = jtag_reset || i_rst;

    always @(posedge jtag_drck or posedge jtag_async_reset) begin
        if (jtag_async_reset) begin
            jtag_q <= 0;
        end else if (jtag_sel && jtag_capture) begin
            jtag_q <= jtag_data;
        end else if (jtag_sel && jtag_shift) begin
            jtag_q <= {jtag_tdi, jtag_q[41:1]};
        end
    end

    always @(posedge jtag_update or posedge jtag_async_reset) begin
        if (jtag_async_reset) begin
            jtag_data <= 0;
        end else if (jtag_sel) begin
            jtag_data <= jtag_q;
        end
    end

    wire [41:0] j_data;
    wire j_data_update;
    cdc_strobed #(42) j_data_cdc (
        .i_clk_a(i_clk),
        .i_clk_b(i_clk),
        .i_data(jtag_data),
        .i_strobe(jtag_update),
        .o_data(j_data),
        .o_strobe(j_data_update)
    );

endmodule