Files
fpga_modem/rtl/util/clog2.vh
2026-02-22 16:03:21 +01:00

10 lines
201 B
Systemverilog

function integer clog2;
input integer value;
integer i;
begin
value = value - 1;
for (i = 0; value > 0; i = i + 1)
value = value >> 1;
clog2 = (i < 1) ? 1 : i;
end
endfunction