Files
fpga_modem/cores/util/conv/conv.core

17 lines
278 B
Core

CAPI=2:
name: joppeb:util:conv:1.0
description: Verilog conversion helper header
filesets:
include:
files:
- conv.vh:
is_include_file: true
file_type: verilogSource
targets:
default:
filesets:
- include