70 lines
1.3 KiB
Verilog
70 lines
1.3 KiB
Verilog
`timescale 1ns/1ps
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module top_generic(
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input wire aclk,
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input wire aresetn,
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output wire led_green,
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output wire led_red,
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output wire[5:0] r2r
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);
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// Clocking
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wire clk_100;
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wire clk_15;
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assign clk_100 = aclk;
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clk_gen clocking(
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.clk_in(clk_100),
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.clk_out_15(clk_15)
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);
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wire [31:0] wb_adr;
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wire [31:0] wb_dat;
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wire [31:0] wb_rdt;
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wire [3:0] wb_sel;
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wire wb_we;
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wire wb_stb;
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wire wb_ack;
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wire [31:0] GPIO;
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assign led_green = GPIO[0];
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assign led_red = GPIO[1];
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assign r2r = GPIO[8:2];
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serving #(
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.memfile("../sw/blinky/blinky.hex"),
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.memsize(8192),
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.sim(1'b0),
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.RESET_STRATEGY("MINI"),
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.WITH_CSR(1)
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) serv (
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.i_clk(clk_15),
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.i_rst(!aresetn),
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.i_timer_irq(1'b0),
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.i_wb_rdt(wb_rdt),
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.i_wb_ack(wb_ack),
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.o_wb_adr(wb_adr),
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.o_wb_dat(wb_dat),
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.o_wb_sel(wb_sel),
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.o_wb_we(wb_we),
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.o_wb_stb(wb_stb)
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);
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wb_gpio #(
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.address(32'h40000000)
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) gpio (
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.i_wb_clk(clk_15),
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.i_wb_rst(!aresetn),
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.i_wb_dat(wb_dat),
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.i_wb_adr(wb_adr),
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.i_wb_we(wb_we),
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.i_wb_stb(wb_stb),
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.i_wb_sel(wb_sel),
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.o_wb_rdt(wb_rdt),
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.o_wb_ack(wb_ack),
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.o_gpio(GPIO)
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);
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endmodule |