Files
fpga_modem/cores/primitive/clkgen/clkgen.core

50 lines
1.1 KiB
Core

CAPI=2:
name: joppeb:primitive:clkgen:1.0
description: Parameterized clock generator wrapper
filesets:
wrapper:
files:
- clkgen.v
file_type: verilogSource
generic:
files:
- clkgen_generic_impl.v
file_type: verilogSource
spartan6:
files:
- clkgen_spartan6.v
file_type: verilogSource
targets:
default:
filesets:
- wrapper
- generic
- spartan6
toplevel: clkgen
parameters:
- CLK_IN_HZ
- CLKFX_DIVIDE
- CLKFX_MULTIPLY
- CLKDV_DIVIDE
parameters:
CLK_IN_HZ:
datatype: int
description: Input clock frequency in Hz
paramtype: vlogparam
CLKFX_DIVIDE:
datatype: int
description: DCM CLKFX divide value
paramtype: vlogparam
CLKFX_MULTIPLY:
datatype: int
description: DCM CLKFX multiply value
paramtype: vlogparam
CLKDV_DIVIDE:
datatype: real
description: DCM CLKDV divide value
paramtype: vlogparam