49 lines
1.2 KiB
Core
49 lines
1.2 KiB
Core
CAPI=2:
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name: joppeb:system:mcu:1.0
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description: basic RISC-V MCU system
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filesets:
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rtl:
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depend:
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- "^award-winning:serv:servile:1.4.0"
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- joppeb:util:clog2
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- joppeb:wb:jtag_wb_bridge
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- joppeb:wb:wb_gpio_banks
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- joppeb:wb:wb_timer
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- joppeb:wb:wb_arbiter
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- joppeb:wb:wb_mux
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files:
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- rtl/mcu.v
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- rtl/mcu_peripherals.v
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file_type: verilogSource
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targets:
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default:
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filesets:
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- rtl
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toplevel: mcu
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parameters:
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- memfile
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- memsize
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- sim
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- jtag
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parameters:
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memfile:
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datatype: str
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description: Memory initialization file passed to the internal RAM
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paramtype: vlogparam
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memsize:
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datatype: int
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description: Internal RAM size in bytes
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paramtype: vlogparam
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sim:
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datatype: int
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description: Enable simulation-friendly RAM initialization behavior
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paramtype: vlogparam
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jtag:
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datatype: int
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description: Enable the JTAG Wishbone bridge and arbiter path
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paramtype: vlogparam
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