CAPI=2:

name: joppeb:system:mcu:1.0
description: basic RISC-V MCU system

filesets:
    rtl:
        depend:
            - "^award-winning:serv:servile:1.4.0"
            - joppeb:util:clog2
            - joppeb:wb:jtag_wb_bridge
            - joppeb:wb:wb_gpio_banks
            - joppeb:wb:wb_timer
            - joppeb:wb:wb_arbiter
            - joppeb:wb:wb_mux
        files:
            - rtl/mcu.v
            - rtl/mcu_peripherals.v
        file_type: verilogSource

targets:
    default:
        filesets:
            - rtl
        toplevel: mcu
        parameters:
            - memfile
            - memsize
            - sim
            - jtag

parameters:
    memfile:
        datatype: str
        description: Memory initialization file passed to the internal RAM
        paramtype: vlogparam
    memsize:
        datatype: int
        description: Internal RAM size in bytes
        paramtype: vlogparam
    sim:
        datatype: int
        description: Enable simulation-friendly RAM initialization behavior
        paramtype: vlogparam
    jtag:
        datatype: int
        description: Enable the JTAG Wishbone bridge and arbiter path
        paramtype: vlogparam