80 lines
2.0 KiB
Verilog
80 lines
2.0 KiB
Verilog
`timescale 1ns/1ps
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// =============================================================================
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// Clock generator
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// Spartan-6 DCM wrapper with parameterized input and output ratios.
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// =============================================================================
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module clkgen_spartan6_impl #(
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parameter integer CLK_IN_HZ = 100000000,
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parameter integer CLKFX_DIVIDE = 20,
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parameter integer CLKFX_MULTIPLY = 3,
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parameter real CLKDV_DIVIDE = 2.0
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)(
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input wire clk_in,
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output wire clk_out
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);
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`ifdef FPGA_SPARTAN6
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localparam real CLKIN_PERIOD_NS = 1000000000.0 / CLK_IN_HZ;
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wire clkfb;
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wire clk0;
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wire clkfx;
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wire locked_unused;
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wire [7:0] status_unused;
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DCM_SP #(
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.CLKDV_DIVIDE(CLKDV_DIVIDE),
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.CLKFX_DIVIDE(CLKFX_DIVIDE),
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.CLKFX_MULTIPLY(CLKFX_MULTIPLY),
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.CLKIN_DIVIDE_BY_2("FALSE"),
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.CLKIN_PERIOD(CLKIN_PERIOD_NS),
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.CLKOUT_PHASE_SHIFT("NONE"),
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.CLK_FEEDBACK("1X"),
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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.PHASE_SHIFT(0),
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.STARTUP_WAIT("FALSE")
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) dcm_sp_i (
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.CLKIN(clk_in),
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.CLKFB(clkfb),
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.CLK0(clk0),
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.CLK90(),
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.CLK180(),
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.CLK270(),
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.CLK2X(),
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.CLK2X180(),
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.CLKFX(clkfx),
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.CLKFX180(),
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.CLKDV(),
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.PSCLK(1'b0),
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.PSEN(1'b0),
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.PSINCDEC(1'b0),
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.PSDONE(),
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.LOCKED(locked_unused),
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.STATUS(status_unused),
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.RST(1'b0),
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.DSSEN(1'b0)
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);
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BUFG clkfb_buf_i (
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.I(clk0),
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.O(clkfb)
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);
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BUFG clkout_buf_i (
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.I(clkfx),
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.O(clk_out)
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);
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`else
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assign clk_out = 1'b0;
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wire _unused_clk_in;
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wire _unused_clkfx_divide;
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wire _unused_clkfx_multiply;
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wire _unused_clkdv_divide;
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assign _unused_clk_in = clk_in;
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assign _unused_clkfx_divide = CLKFX_DIVIDE[0];
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assign _unused_clkfx_multiply = CLKFX_MULTIPLY[0];
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assign _unused_clkdv_divide = (CLKDV_DIVIDE != 0.0);
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`endif
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endmodule
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