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joppe
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fpga_modem
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6f680377db27f97ece2a269c524dc3f24f383f90
fpga_modem
/
sim
/
overrides
History
Joppe Blondel
8f4e887b9d
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
..
clk_gen.v
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
jtag_if.v
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
sigmadelta_sampler.v
Added lvds and sampler
2025-10-08 18:01:03 +02:00
