64 lines
1.7 KiB
Verilog
64 lines
1.7 KiB
Verilog
`default_nettype none
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module wb_gpio_banks #(
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parameter integer NUM_BANKS = 4,
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parameter [31:0] BASE_ADDR = 32'h8000_0000
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) (
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input wire i_wb_clk,
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input wire i_wb_rst,
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input wire [31:0] i_wb_adr,
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input wire [31:0] i_wb_dat,
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input wire [3:0] i_wb_sel,
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input wire i_wb_we,
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input wire i_wb_stb,
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input wire [NUM_BANKS*32-1:0] i_gpio,
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output reg [31:0] o_wb_rdt,
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output reg o_wb_ack,
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output wire [NUM_BANKS*32-1:0] o_gpio
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);
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wire [NUM_BANKS-1:0] bank_sel;
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wire [NUM_BANKS-1:0] bank_stb;
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wire [NUM_BANKS*32-1:0] bank_rdt;
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wire [NUM_BANKS-1:0] bank_ack;
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genvar gi;
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generate
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for (gi = 0; gi < NUM_BANKS; gi = gi + 1) begin : gen_gpio
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localparam [31:0] BANK_ADDR = BASE_ADDR + (gi * 4);
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assign bank_sel[gi] = (i_wb_adr == BANK_ADDR);
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assign bank_stb[gi] = i_wb_stb & bank_sel[gi];
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wb_gpio #(
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.address(BANK_ADDR)
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) u_gpio (
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.i_wb_clk(i_wb_clk),
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.i_wb_rst(i_wb_rst),
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.i_wb_adr(i_wb_adr),
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.i_wb_dat(i_wb_dat),
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.i_wb_sel(i_wb_sel),
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.i_wb_we(i_wb_we),
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.i_wb_stb(bank_stb[gi]),
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.i_gpio(i_gpio[gi*32 +: 32]),
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.o_wb_rdt(bank_rdt[gi*32 +: 32]),
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.o_wb_ack(bank_ack[gi]),
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.o_gpio(o_gpio[gi*32 +: 32])
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);
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end
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endgenerate
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integer bi;
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always @* begin
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o_wb_rdt = 32'h0000_0000;
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o_wb_ack = 1'b0;
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for (bi = 0; bi < NUM_BANKS; bi = bi + 1) begin
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if (bank_sel[bi]) begin
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o_wb_rdt = bank_rdt[bi*32 +: 32];
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o_wb_ack = bank_ack[bi];
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end
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end
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end
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endmodule
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