152 lines
3.1 KiB
Verilog
152 lines
3.1 KiB
Verilog
// SPDX-License-Identifier: ISC
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`default_nettype none
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module qerv_immdec
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(
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input wire i_clk,
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//State
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input wire i_cnt_en,
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input wire i_cnt_done,
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//Control
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input wire [3:0] i_immdec_en,
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input wire i_csr_imm_en,
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input wire [3:0] i_ctrl,
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output wire [4:0] o_rd_addr,
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output wire [4:0] o_rs1_addr,
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output wire [4:0] o_rs2_addr,
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//Data
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output wire [3:0] o_csr_imm,
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output wire [3:0] o_imm,
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//External
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input wire i_wb_en,
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input wire [31:7] i_wb_rdt);
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reg [4:0] rd_addr;
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reg [4:0] rs1_addr;
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reg [4:0] rs2_addr;
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reg i31;
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reg i30;
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reg i29;
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reg i28;
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reg i27;
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reg i26;
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reg i25;
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reg i24;
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reg i23;
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reg i22;
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reg i21;
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reg i20;
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reg i19;
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reg i18;
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reg i17;
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reg i16;
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reg i15;
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reg i14;
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reg i13;
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reg i12;
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reg i11;
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reg i10;
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reg i9;
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reg i8;
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reg i7;
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reg i7_2;
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reg i20_2;
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wire signbit = i31 & !i_csr_imm_en;
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assign o_csr_imm[3] = i18;
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assign o_csr_imm[2] = i17;
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assign o_csr_imm[1] = i16;
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assign o_csr_imm[0] = i15;
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assign o_rd_addr = rd_addr;
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assign o_rs1_addr = rs1_addr;
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assign o_rs2_addr = rs2_addr;
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always @(posedge i_clk) begin
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if (i_wb_en) begin
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//Common
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i31 <= i_wb_rdt[31];
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//Bit lane 3
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i19 <= i_wb_rdt[19];
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i15 <= i_wb_rdt[15];
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i20 <= i_wb_rdt[20];
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i7 <= i_wb_rdt[7];
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i27 <= i_wb_rdt[27];
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i23 <= i_wb_rdt[23];
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i10 <= i_wb_rdt[10];
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//Bit lane 2
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i22 <= i_wb_rdt[22];
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i9 <= i_wb_rdt[ 9];
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i26 <= i_wb_rdt[26];
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i30 <= i_wb_rdt[30];
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i14 <= i_wb_rdt[14];
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i18 <= i_wb_rdt[18];
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//Bit lane 1
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i21 <= i_wb_rdt[21];
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i8 <= i_wb_rdt[ 8];
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i25 <= i_wb_rdt[25];
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i29 <= i_wb_rdt[29];
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i13 <= i_wb_rdt[13];
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i17 <= i_wb_rdt[17];
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//Bit lane 0
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i11 <= i_wb_rdt[11];
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i7_2 <= i_wb_rdt[7 ];
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i20_2 <= i_wb_rdt[20];
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i24 <= i_wb_rdt[24];
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i28 <= i_wb_rdt[28];
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i12 <= i_wb_rdt[12];
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i16 <= i_wb_rdt[16];
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rd_addr <= i_wb_rdt[11:7];
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rs1_addr <= i_wb_rdt[19:15];
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rs2_addr <= i_wb_rdt[24:20];
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end
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if (i_cnt_en) begin
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//Bit lane 3
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i10 <= i27;
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i23 <= i27;
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i27 <= i_ctrl[2] ? i7 : i_ctrl[1] ? signbit : i20;
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i7 <= signbit;
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i20 <= i15;
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i15 <= i19;
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i19 <= i_ctrl[3] ? signbit : i23;
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//Bit lane 2
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i22 <= i26;
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i9 <= i26;
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i26 <= i30;
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i30 <= (i_ctrl[1] | i_ctrl[2]) ? signbit : i14;
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i14 <= i18;
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i18 <= i_ctrl[3] ? signbit : i22;
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//Bit lane 1
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i21 <= i25;
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i8 <= i25;
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i25 <= i29;
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i29 <= (i_ctrl[1] | i_ctrl[2]) ? signbit : i13;
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i13 <= i17;
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i17 <= i_ctrl[3] ? signbit : i21;
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//Bit lane 0
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i7_2 <= i11;
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i11 <= i28;
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i20_2 <= i24;
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i24 <= i28;
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i28 <= (i_ctrl[1] | i_ctrl[2]) ? signbit : i12;
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i12 <= i16;
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i16 <= i_ctrl[3] ? signbit : i20_2;
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end
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end
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assign o_imm[3] = (i_cnt_done ? signbit : (i_ctrl[0] ? i10 : i23));
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assign o_imm[2] = i_ctrl[0] ? i9 : i22;
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assign o_imm[1] = i_ctrl[0] ? i8 : i21;
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assign o_imm[0] = i_ctrl[0] ? i7_2 : i20_2;
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endmodule |