70 lines
1.8 KiB
Verilog
70 lines
1.8 KiB
Verilog
`timescale 1 ns/1 ps
|
|
// =============================================================================
|
|
// cdc_req_resp
|
|
// Bidirectional channel made from two cdc_strobe_data mailboxes.
|
|
// =============================================================================
|
|
module cdc_req_resp #(
|
|
parameter integer REQ_W = 32,
|
|
parameter integer RESP_W = 32,
|
|
parameter integer STABLE_SAMPLES = 2
|
|
)(
|
|
// Side A (e.g., JTAG/TCK)
|
|
input wire a_clk,
|
|
input wire a_rst,
|
|
|
|
input wire a_req_pulse,
|
|
input wire [REQ_W-1:0] a_req_data,
|
|
output wire a_req_busy,
|
|
output wire a_req_accepted,
|
|
|
|
output wire a_resp_pulse,
|
|
output wire [RESP_W-1:0] a_resp_data,
|
|
|
|
// Side B (e.g., system/i_clk)
|
|
input wire b_clk,
|
|
input wire b_rst,
|
|
|
|
output wire b_req_pulse,
|
|
output wire [REQ_W-1:0] b_req_data,
|
|
|
|
input wire b_resp_pulse,
|
|
input wire [RESP_W-1:0] b_resp_data,
|
|
output wire b_resp_busy,
|
|
output wire b_resp_accepted
|
|
);
|
|
|
|
cdc_strobe_data #(
|
|
.WIDTH(REQ_W),
|
|
.STABLE_SAMPLES(STABLE_SAMPLES)
|
|
) u_req (
|
|
.s_clk(a_clk),
|
|
.s_rst(a_rst),
|
|
.s_pulse(a_req_pulse),
|
|
.s_data(a_req_data),
|
|
.s_busy(a_req_busy),
|
|
.s_accepted(a_req_accepted),
|
|
|
|
.d_clk(b_clk),
|
|
.d_rst(b_rst),
|
|
.d_pulse(b_req_pulse),
|
|
.d_data(b_req_data)
|
|
);
|
|
|
|
cdc_strobe_data #(
|
|
.WIDTH(RESP_W),
|
|
.STABLE_SAMPLES(STABLE_SAMPLES)
|
|
) u_resp (
|
|
.s_clk(b_clk),
|
|
.s_rst(b_rst),
|
|
.s_pulse(b_resp_pulse),
|
|
.s_data(b_resp_data),
|
|
.s_busy(b_resp_busy),
|
|
.s_accepted(b_resp_accepted),
|
|
|
|
.d_clk(a_clk),
|
|
.d_rst(a_rst),
|
|
.d_pulse(a_resp_pulse),
|
|
.d_data(a_resp_data)
|
|
);
|
|
|
|
endmodule |