64 lines
1.4 KiB
Verilog
64 lines
1.4 KiB
Verilog
`timescale 1ns/1ps
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module toplevel_tb;
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reg clk;
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reg reset_n;
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reg button;
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wire led;
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toplevel m_toplevel(
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.clk(clk),
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.reset_n(reset_n),
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.button(button),
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.led(led),
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.adc1_A(1'b0),
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.adc1_B(1'b0)
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);
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initial begin
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$dumpfile("toplevel_tb.vcd");
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$dumpvars (0, toplevel_tb);
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clk <= 1'b0;
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reset_n <= 1'b0;
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button <= 1'b0;
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#50 reset_n <= 1'b1;
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// Wait for clk 120 starts
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@(posedge toplevel_tb.m_toplevel.clk_120);
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#78 button <= 1'b1;
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#185 button <= 1'b0;
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#2000000
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$finish;
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end
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always #18.5 clk = ~clk;
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// Simulation stuff
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// PLL quickstart
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`ifndef TIMING_SIM
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reg tb_pll_clk = 1'b0;
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always #4.15 tb_pll_clk = ~tb_pll_clk;
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initial begin
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@(posedge reset_n);
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repeat (8) @(posedge clk); // give the model time to measure CLKIN
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force toplevel_tb.m_toplevel.m_pll.pllvr_inst.LOCK = 1'b1;
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force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUT = tb_pll_clk;
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force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUTP = tb_pll_clk;
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force toplevel_tb.m_toplevel.m_pll.pllvr_inst.RESET = 1'b1;
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end
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`endif
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// SDF annotation
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`ifdef TIMING_SIM
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initial begin
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$sdf_annotate("impl/pnr/modem.sdf", m_toplevel, , , "MAXIMUM");
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end
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`endif
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endmodule |