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fpga_modem/IP/gw_clkdiv8/gw_clkdiv8_tmp.v
2025-10-01 21:15:20 +02:00

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//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Template file for instantiation
//Tool Version: V1.9.12
//Part Number: GW1NSR-LV4CQN48PC7/I6
//Device: GW1NSR-4C
//Created Time: Wed Oct 1 18:23:11 2025
//Change the instance name and port connections to the signal names
//--------Copy here to design--------
gw_clkdiv8 your_instance_name(
.clkout(clkout), //output clkout
.hclkin(hclkin), //input hclkin
.resetn(resetn) //input resetn
);
//--------Copy end-------------------