13 lines
338 B
Verilog
13 lines
338 B
Verilog
`timescale 1ns/1ps
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// =============================================================================
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// Clock generator/PLL
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// Simple pass through
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// =============================================================================
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module clk_gen(
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input wire clk_in,
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output wire clk_out_15
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);
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assign clk_out_15 = clk_in;
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endmodule
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