joppe/fpga_modem
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49b8a774807a867e46abd824d6713c2d63d2d369
fpga_modem/rtl/arch/spartan-6
History
Joppe Blondel eb7caaf2c5 Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
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clk_gen.v
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
lvds_comparator.v
Added lvds and sampler
2025-10-08 18:01:03 +02:00