14 lines
523 B
XML
14 lines
523 B
XML
<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE gowin-fpga-project>
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<Project>
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<Template>FPGA</Template>
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<Version>5</Version>
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<Device name="GW1NSR-4C" pn="GW1NSR-LV4CQN48PC7/I6">gw1nsr4c-009</Device>
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<FileList>
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<File path="HW/toplevel.v" type="file.verilog" enable="1"/>
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<File path="IP/ge_pllvr/gw_pllvr.v" type="file.verilog" enable="1"/>
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<File path="CON/io.cst" type="file.cst" enable="1"/>
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<File path="CON/timing.sdc" type="file.sdc" enable="1"/>
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</FileList>
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</Project>
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