20 lines
341 B
Verilog
20 lines
341 B
Verilog
`timescale 1ns/1ps
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module toplevel(
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input wire clk,
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input wire reset_n,
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input wire button,
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output wire led
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);
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reg led_v;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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led_v <= 1'b0;
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end else begin
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led_v <= button;
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end
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end
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assign led = led_v;
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endmodule |