TODO: think of other way of shifting in data. Bit errors make uploading difficult
100 lines
2.0 KiB
ArmAsm
100 lines
2.0 KiB
ArmAsm
.section .text.init
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.globl _start
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.type _start, @function
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_start:
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la sp, __stack_top
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# Zero .bss
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la t0, __bss_start
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la t1, __bss_end
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1:
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bgeu t0, t1, 2f
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sw zero, 0(t0)
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addi t0, t0, 4
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j 1b
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2:
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call main
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3:
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j 3b
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.size _start, .-_start
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.section .text
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.globl trap_entry
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.type trap_entry, @function
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trap_entry:
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# Save full integer context (except x0/x2) because an interrupt can
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# preempt code with live values in any register, not just caller-saved.
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addi sp, sp, -128
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sw ra, 124(sp)
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sw gp, 120(sp)
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sw tp, 116(sp)
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sw t0, 112(sp)
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sw t1, 108(sp)
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sw t2, 104(sp)
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sw s0, 100(sp)
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sw s1, 96(sp)
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sw a0, 92(sp)
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sw a1, 88(sp)
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sw a2, 84(sp)
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sw a3, 80(sp)
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sw a4, 76(sp)
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sw a5, 72(sp)
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sw a6, 68(sp)
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sw a7, 64(sp)
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sw s2, 60(sp)
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sw s3, 56(sp)
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sw s4, 52(sp)
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sw s5, 48(sp)
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sw s6, 44(sp)
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sw s7, 40(sp)
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sw s8, 36(sp)
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sw s9, 32(sp)
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sw s10, 28(sp)
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sw s11, 24(sp)
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sw t3, 20(sp)
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sw t4, 16(sp)
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sw t5, 12(sp)
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sw t6, 8(sp)
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csrr t0, mcause
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li t1, 0x80000007 # machine timer interrupt (RV32)
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bne t0, t1, 1f
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call timer_isr # C function that ACKs/clears the timer so i_timer_irq goes low
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1:
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lw t6, 8(sp)
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lw t5, 12(sp)
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lw t4, 16(sp)
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lw t3, 20(sp)
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lw s11, 24(sp)
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lw s10, 28(sp)
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lw s9, 32(sp)
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lw s8, 36(sp)
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lw s7, 40(sp)
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lw s6, 44(sp)
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lw s5, 48(sp)
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lw s4, 52(sp)
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lw s3, 56(sp)
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lw s2, 60(sp)
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lw a7, 64(sp)
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lw a6, 68(sp)
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lw a5, 72(sp)
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lw a4, 76(sp)
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lw a3, 80(sp)
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lw a2, 84(sp)
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lw a1, 88(sp)
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lw a0, 92(sp)
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lw s1, 96(sp)
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lw s0, 100(sp)
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lw t2, 104(sp)
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lw t1, 108(sp)
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lw t0, 112(sp)
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lw tp, 116(sp)
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lw gp, 120(sp)
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lw ra, 124(sp)
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addi sp, sp, 128
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mret
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