Files
fpga_modem/project.cfg
2025-10-06 16:49:28 +02:00

45 lines
1.2 KiB
INI

[project]
name = modem
version = 0.1
out_dir = out
build_dir = build
[server]
hostname = localhost
port = 2020
privkey = /home/joppe/.ssh/id_rsa
pubkey = /home/joppe/.ssh/id_rsa.pub
[target.synth]
toolchain = ISE
# Toolchain settings
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
toplevel = top_generic
xst_opts = -vlgincdir rtl
#ngdbuild_opts =
#map_opts =
#par_opts =
#netgen_opts =
#bitgen_opts =
#trce_opts =
# Files
#files_vhdl =
files_verilog = rtl/toplevel/top_generic.v
rtl/core/nco_q15.v
files_con = boards/mimas_v1/constraints.ucf
files_other = rtl/util/conv.vh
[target.sim]
toolchain = iverilog
runtime = all
toplevel = tb_nco_q15
ivl_opts = -Irtl
#vvp_opts =
# Files
#files_sysverilog =
files_verilog = sim/tb/tb_nco_q15.v
rtl/core/nco_q15.v
files_other = rtl/util/conv.vh