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fpga_modem
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Joppe Blondel
1c37d384c2
Added everything from the other system
2026-02-28 21:46:59 +01:00
cores
Added everything from the other system
2026-02-28 21:46:59 +01:00
fusesoc_libraries
Added everything from the other system
2026-02-28 21:46:59 +01:00
.gitignore
Initial commit
2026-02-28 13:52:08 +01:00
.gitmodules
Added everything from the other system
2026-02-28 21:46:59 +01:00
fusesoc.conf
Added everything from the other system
2026-02-28 21:46:59 +01:00
Description
No description provided
1.1
MiB
Languages
Verilog
69.4%
C++
15.9%
Python
8.2%
SystemVerilog
2%
C
1.3%
Other
3.2%
