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joppe
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fpga_modem
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105dbed8e4e7015a786bd827dd2a4fbaa19666ae
fpga_modem
/
sim
/
tb
History
Joppe Blondel
3a9b2acf9e
New wishbone-jtag bridge
2026-02-27 15:56:56 +01:00
..
tb_cdc_strobe_data.v
New wishbone-jtag bridge
2026-02-27 15:56:56 +01:00
tb_jtag_wb_bridge.v
New wishbone-jtag bridge
2026-02-27 15:56:56 +01:00
tb_mul_const.v
Added mul tb and fixed
2025-10-19 16:18:40 +02:00
tb_nco_q15.v
Improved NCO: 200MHz
2025-10-06 16:25:40 +02:00
tb_serving.v
Added soclet with gpio banks to top
2026-02-22 20:00:42 +01:00
tb_sigmadelta.v
Combined all sigmadelta things to one input block
2025-10-19 20:03:51 +02:00
tb_top_generic.v
TImer working with tests
2026-02-25 22:01:28 +01:00
tb_wb_timer.v
Added timer, still wip
2026-02-25 20:54:12 +01:00