37 lines
724 B
Verilog
37 lines
724 B
Verilog
`timescale 1ns/1ps
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module tb_sigmadelta();
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// Clock and reset generation
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reg clk;
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reg resetn;
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initial clk <= 1'b0;
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initial resetn <= 1'b0;
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always #6.667 clk <= !clk;
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initial #40 resetn <= 1'b1;
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// Default run
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initial begin
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$dumpfile("out.vcd");
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$dumpvars;
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#2_000_000
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$finish;
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end;
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wire sd_a;
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wire sd_b;
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wire sd_o;
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wire signed [15:0] decimated_q15;
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wire decimated_valid;
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sigmadelta_input #(
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.R_OHM(3300),
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.C_PF(220)
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) dut(
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.clk_15(clk), .resetn(resetn),
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.adc_a(sd_a), .adc_b(sd_b), .adc_o(sd_o),
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.signal_q15(decimated_q15),
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.signal_valid(decimated_valid)
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);
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endmodule
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