`timescale 1ns/1ps

module tb_sigmadelta();
    // Clock and reset generation
    reg clk;
    reg resetn;
    initial clk <= 1'b0;
    initial resetn <= 1'b0;
    always #6.667 clk <= !clk;
    initial #40 resetn <= 1'b1;

    // Default run
    initial begin
        $dumpfile("out.vcd");
        $dumpvars;
        #2_000_000
        $finish;
    end;

    wire sd_a;
    wire sd_b;
    wire sd_o;
    wire signed [15:0] decimated_q15;
    wire decimated_valid;

    sigmadelta_input #(
        .R_OHM(3300),
        .C_PF(220)
    ) dut(
        .clk_15(clk), .resetn(resetn),
        .adc_a(sd_a), .adc_b(sd_b), .adc_o(sd_o),
        .signal_q15(decimated_q15),
        .signal_valid(decimated_valid)
    );

endmodule