13 lines
337 B
Verilog
13 lines
337 B
Verilog
`timescale 1ns/1ps
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// =============================================================================
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// LVDS comparator
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// Simple pass-though model
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// =============================================================================
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module lvds_comparator(
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input wire a,
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input wire b,
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output wire o
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);
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assign o = a;
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endmodule |