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fpga_modem/rtl/core
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Joppe Blondel 49b8a77480 Combined all sigmadelta things to one input block
2025-10-19 20:03:51 +02:00
..
clk_gen.v
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
decimate_by_r_q15.v
Added decimation
2025-10-19 17:26:09 +02:00
lpf_iir_q15_k.v
Added K IIR lpf filter
2025-10-19 17:02:29 +02:00
lvds_comparator.v
Added lvds and sampler
2025-10-08 18:01:03 +02:00
mul_const.v
Added mul tb and fixed
2025-10-19 16:18:40 +02:00
nco_q15.v
Improved NCO: 200MHz
2025-10-06 16:25:40 +02:00
sigmadelta_input_q15.v
Combined all sigmadelta things to one input block
2025-10-19 20:03:51 +02:00
sigmadelta_rcmodel_q15.v
Added mul tb and fixed
2025-10-19 16:18:40 +02:00
sigmadelta_sampler.v
Added lvds and sampler
2025-10-08 18:01:03 +02:00
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