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joppe
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fpga_modem
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f2f96448303e0e53c4c705fe2746ee23f1d23bc3
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2 Commits
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Joppe Blondel
5e951f9b61
Working SERV cpu
2026-02-22 18:48:17 +01:00
Joppe Blondel
eb7caaf2c5
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00