joppe/fpga_modem
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43 Commits 1 Branch 0 Tags
8cccea85e0945f3503b5b51a297a922c8cf19e7f
Commit Graph
13 Commits
Author SHA1 Message Date
Joppe Blondel 8cccea85e0 Added adc->dac path test 2026-03-04 23:35:02 +01:00
Joppe Blondel 4e3521e94a Added missing signal modules 2026-03-02 19:28:36 +01:00
Joppe Blondel 50f71a2985 Added new master checker and changed to synchronous reset checks 2026-03-02 18:02:47 +01:00
Joppe Blondel 628972ccaa New slave checker and updated gpio and gpio_banks 2026-03-02 13:48:30 +01:00
Joppe Blondel a6a5c6ea3f Made timer synthesizable 2026-03-01 21:11:08 +01:00
Joppe Blondel 5b940758b6 Added formal verification set to timer internally 2026-03-01 21:00:57 +01:00
Joppe Blondel abe0668787 new timer 2026-03-01 17:19:46 +01:00
Joppe Blondel 7b46ae5e87 Some cleanup and added formal for the banks and timer 2026-03-01 14:12:12 +01:00
Joppe Blondel 8289b0d090 Added wb formal script and added other sby tasks 2026-03-01 13:52:41 +01:00
Joppe Blondel cf483decad Added everything from the other system 2026-02-28 21:52:06 +01:00
Joppe Blondel 907f244b24 Added libjtag_wb_bridge 2026-02-28 18:39:50 +01:00
Joppe Blondel cf7e03b9fe Added some stuff from modem and added formal 2026-02-28 18:23:39 +01:00
Joppe Blondel fa641b1eab Initial commit 
Added nco_q15
 2026-02-28 13:52:08 +01:00