joppe/fpga_modem
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
14 Commits 2 Branches 0 Tags
master
Commit Graph

2 Commits

Author SHA1 Message Date
Joppe Blondel
49b8a77480 Combined all sigmadelta things to one input block 2025-10-19 20:03:51 +02:00
Joppe Blondel
eb7caaf2c5 Added PLL/clock generator and SD RC model 2025-10-19 15:36:55 +02:00