Added PLL/clock generator and SD RC model

rtl/toplevel/top_generic.v

@@ -9,10 +9,18 @@ module top_generic(
 
     output wire[5:0] r2r
 );
-    `include "util/conv.vh"
+    `include "conv.vh"
     assign led_green = 1'b0;
     assign led_red = 1'b0;
 
+    // Clocking
+    wire clk_100;
+    wire clk_15;
+    assign clk_100 = aclk;
+    clk_gen clocking(
+        .clk_in(clk_100),
+        .clk_out_15(clk_15)
+    );
 
     reg [11:0] count;
     localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz