Added PLL/clock generator and SD RC model

rtl/core/clk_gen.v

@@ -0,0 +1,12 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// Clock generator/PLL
+// Simple pass through
+// =============================================================================
+module clk_gen(
+    input wire clk_in,
+    output wire clk_out_15
+);
+   assign clk_out_15 = clk_in;
+endmodule