Added PLL/clock generator and SD RC model
This commit is contained in:
Joppe Blondel
148
rtl/arch/spartan-6/clk_gen.v
Executable file
148
rtl/arch/spartan-6/clk_gen.v
Executable file
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// file: clk_gen.v
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//
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// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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//
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//----------------------------------------------------------------------------
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// User entered comments
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//----------------------------------------------------------------------------
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// None
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//
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//----------------------------------------------------------------------------
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// "Output Output Phase Duty Pk-to-Pk Phase"
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// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
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//----------------------------------------------------------------------------
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// CLK_OUT1____15.000______0.000______50.0_____1533.333____150.000
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//
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//----------------------------------------------------------------------------
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// "Input Clock Freq (MHz) Input Jitter (UI)"
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//----------------------------------------------------------------------------
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// __primary_________100.000____________0.010
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`timescale 1ps/1ps
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(* CORE_GENERATION_INFO = "clk_gen,clk_wiz_v3_6,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
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module clk_gen
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(// Clock in ports
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input clk_in,
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// Clock out ports
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output clk_out_15
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);
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// Input buffering
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//------------------------------------
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// BUFG clkin1_buf
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// (.O (clkin1),
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// .I (clk_in));
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assign clkin1 = clk_in;
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// Clocking primitive
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//------------------------------------
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// Instantiation of the DCM primitive
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// * Unused inputs are tied off
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// * Unused outputs are labeled unused
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wire psdone_unused;
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wire locked_int;
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wire [7:0] status_int;
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wire clkfb;
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wire clk0;
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wire clkfx;
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DCM_SP
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#(.CLKDV_DIVIDE (2.000),
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.CLKFX_DIVIDE (20),
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.CLKFX_MULTIPLY (3),
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.CLKIN_DIVIDE_BY_2 ("FALSE"),
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.CLKIN_PERIOD (10.0),
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.CLKOUT_PHASE_SHIFT ("NONE"),
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.CLK_FEEDBACK ("1X"),
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.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
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.PHASE_SHIFT (0),
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.STARTUP_WAIT ("FALSE"))
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dcm_sp_inst
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// Input clock
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(.CLKIN (clkin1),
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.CLKFB (clkfb),
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// Output clocks
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.CLK0 (clk0),
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.CLK90 (),
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.CLK180 (),
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.CLK270 (),
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.CLK2X (),
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.CLK2X180 (),
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.CLKFX (clkfx),
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.CLKFX180 (),
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.CLKDV (),
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// Ports for dynamic phase shift
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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// Other control and status signals
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.LOCKED (locked_int),
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.STATUS (status_int),
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.RST (1'b0),
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// Unused pin- tie low
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.DSSEN (1'b0));
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// Output buffering
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//-----------------------------------
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BUFG clkf_buf
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(.O (clkfb),
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.I (clk0));
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BUFG clkout1_buf
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(.O (clk_out_15),
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.I (clkfx));
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endmodule
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12
rtl/core/clk_gen.v
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12
rtl/core/clk_gen.v
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`timescale 1ns/1ps
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// =============================================================================
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// Clock generator/PLL
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// Simple pass through
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// =============================================================================
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module clk_gen(
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input wire clk_in,
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output wire clk_out_15
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);
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assign clk_out_15 = clk_in;
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endmodule
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65
rtl/core/mul_const.v
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65
rtl/core/mul_const.v
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`timescale 1ns/1ps
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// =============================================================================
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// Multiply a value by a constant
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// Use a shift-add algorithm instead of a multiplier
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// parameters:
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// -- W : data width
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// -- C : constant
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// inout:
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// -- x : input of width W
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// -- y : output of widht 2W
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// =============================================================================
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module mul_const_shiftadd#(
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parameter integer W = 16,
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parameter integer C = 16'sh7fff
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)(
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input wire signed [W-1:0] x,
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output wire signed [2*W-1:0] y
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);
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// Absolute value and sign of C
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localparam integer C_NEG = (C < 0) ? 1 : 0;
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localparam integer C_ABS = (C < 0) ? -C : C;
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// Find MSB index of C_ABS to size the network
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function integer msb_index;
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input integer v;
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integer i;
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begin
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msb_index = -1;
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for (i = 0; i < 32; i = i + 1)
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if (v >> i) msb_index = i;
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end
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endfunction
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localparam integer I_MAX = (C_ABS == 0) ? 0 : msb_index(C_ABS);
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// Partial products
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wire signed [W+I_MAX:0] part [0:I_MAX];
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genvar i;
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generate
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for (i = 0; i <= I_MAX; i = i + 1) begin : GEN_PARTS
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assign part[i] = (C_ABS[i]) ? ($signed(x) <<< i) : { (W+I_MAX+1){1'b0} };
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end
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endgenerate
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// Adder chain (simple; replace with tree if you want higher performance)
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wire signed [W+I_MAX:0] sum [0:I_MAX];
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generate
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if (I_MAX == 0) begin
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assign sum[0] = part[0];
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end else begin
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assign sum[0] = part[0];
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for (i = 1; i <= I_MAX; i = i + 1) begin : GEN_SUM
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assign sum[i] = sum[i-1] + part[i];
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end
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end
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endgenerate
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// Apply sign of C
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wire signed [W+I_MAX:0] mag = (I_MAX==0) ? part[0] : sum[I_MAX];
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wire signed [W+I_MAX:0] prod = C_NEG ? -mag : mag;
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// Stretch to fixed y width (truncate/extend as you wish outside)
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assign y = prod;
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endmodule
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47
rtl/core/sigmadelta_rcmodel_q15.v
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47
rtl/core/sigmadelta_rcmodel_q15.v
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`timescale 1ns/1ps
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// =============================================================================
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// RC model to convert sigma delta samples to Q1.15
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// Models the RC circuit on the outside of the FPGA
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// Uses: Yn+1 = Yn + (sd - Yn)*(1-exp(-T/RC))
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// parameters:
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// -- alpha_q15 : the 1-exp(-T/RC), defaults to R=3k3, C=220p and T=1/15MHz
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// rounded to only use two bits (0b3b -> 0b00), the less
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// bits the better
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// inout:
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// -- clk : input clock
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// -- resetn : reset signal
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// -- sd_sample : 1 bit sample output from sd sampler
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// -- sample_q15 : output samples in q1.15
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// =============================================================================
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module sigmadelta_rcmodel_q15 #(
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parameter integer alpha_q15 = 16'sh0b00
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)(
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input wire clk,
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input wire resetn,
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input wire sd_sample,
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output wire [15:0] sample_q15
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);
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reg signed [15:0] y_q15;
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wire signed [15:0] sd_q15 = sd_sample ? 16'sh7fff : 16'sh0000;
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wire signed [15:0] e_q15 = sd_q15 - y_q15;
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wire signed [31:0] prod_q30;
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// Use shift-add algorithm for multiplication
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mul_const_shiftadd #(.C(alpha_q15)) alpha_times_e (e_q15, prod_q30);
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wire signed [15:0] y_next_q15 = y_q15 + (prod_q30>>>15);
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// clamp to [0, 0x7FFF] (keeps signal view tidy)
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function signed [15:0] clamp01_q15(input signed [15:0] v);
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if (v < 16'sd0000) clamp01_q15 = 16'sd0000;
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else if (v > 16'sh7FFF) clamp01_q15 = 16'sh7FFF;
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else clamp01_q15 = v;
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endfunction
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always @(posedge clk or negedge resetn) begin
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if (!resetn) y_q15 <= 16'sd0000;
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else y_q15 <= clamp01_q15(y_next_q15);
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end
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assign sample_q15 = y_q15;
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endmodule
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@@ -9,10 +9,18 @@ module top_generic(
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output wire[5:0] r2r
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);
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`include "util/conv.vh"
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`include "conv.vh"
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assign led_green = 1'b0;
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assign led_red = 1'b0;
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// Clocking
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wire clk_100;
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wire clk_15;
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assign clk_100 = aclk;
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clk_gen clocking(
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.clk_in(clk_100),
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.clk_out_15(clk_15)
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);
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reg [11:0] count;
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localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz
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70
rtl/util/rc_alpha_q15.vh
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70
rtl/util/rc_alpha_q15.vh
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// rc_alpha_q15.vh
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// Plain Verilog-2001 constant function: R(ohm), C(pF), Fs(Hz) -> alpha_q15 (Q1.15)
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// Uses fixed-point approximation: 1 - exp(-x) ≈ x - x^2/2 + x^3/6, where x = 1/(Fs*R*C)
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// All integer math; suitable for elaboration-time constant folding (e.g., XST).
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`ifndef RC_ALPHA_Q15_VH
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`define RC_ALPHA_Q15_VH
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function integer alpha_q15_from_rc;
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input integer R_OHM; // resistance in ohms
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input integer C_PF; // capacitance in picofarads
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input integer FS_HZ; // sampling frequency in Hz
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integer N; // fractional bits for x (QN)
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reg [127:0] num_1e12_sllN;
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reg [127:0] denom_u;
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reg [127:0] x_qN; // x in QN
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reg [255:0] x2; // x^2 in Q(2N)
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reg [383:0] x3; // x^3 in Q(3N)
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integer term1_q15; // x -> Q1.15
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integer term2_q15; // x^2/2 -> Q1.15
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integer term3_q15; // x^3/6 -> Q1.15
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integer acc; // accumulator for result
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begin
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// Choose QN for x. N=24 is a good balance for accuracy/width.
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N = 24;
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// x = 1 / (Fs * R * C) with C in pF ==> x = 1e12 / (Fs * R * C_PF)
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// x_qN = round( x * 2^N ) = round( (1e12 << N) / denom )
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num_1e12_sllN = 128'd1000000000000 << N;
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// denom = Fs * R * C_PF (fits in 64..96 bits for typical values)
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denom_u = 0;
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denom_u = denom_u + FS_HZ[127:0];
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denom_u = denom_u * R_OHM[127:0];
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denom_u = denom_u * C_PF[127:0];
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// rounded divide for x_qN
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x_qN = (num_1e12_sllN + (denom_u >> 1)) / denom_u;
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// Powers
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x2 = x_qN * x_qN; // 128x128 -> 256
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x3 = x2 * x_qN; // 256x128 -> 384
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// term1 = x -> shift from QN to Q15
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term1_q15 = (x_qN >> (N - 15)) & 16'hFFFF;
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// term2 = x^2 / 2 -> shift from Q(2N) to Q15 and divide by 2
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term2_q15 = (x2 >> (2*N - 15 + 1)) & 16'hFFFF;
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// term3 = x^3 / 6 -> shift from Q(3N) to Q15, then divide by 6 (rounded)
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begin : gen_term3
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reg [383:0] tmp_q15_wide;
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reg [383:0] tmp_div6;
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tmp_q15_wide = (x3 >> (3*N - 15));
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tmp_div6 = (tmp_q15_wide + 6'd3) / 6; // +3 for rounding
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term3_q15 = tmp_div6[15:0];
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end
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// Combine: alpha_q15 = x - x^2/2 + x^3/6 ; clamp to [0, 0x7FFF]
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acc = term1_q15 - term2_q15 + term3_q15;
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if (acc < 0) acc = 0;
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else if (acc > 16'h7FFF) acc = 16'h7FFF;
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alpha_q15_from_rc = acc;
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end
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endfunction
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`endif
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