Added PLL/clock generator and SD RC model

project.cfg

@@ -12,38 +12,43 @@ pubkey              = /home/joppe/.ssh/id_rsa.pub
 
 [target.synth]
 toolchain           = ISE
-# Toolchain settings
 family              = spartan6
 device              = xc6slx9
 package             = tqg144
 speedgrade          = -2
 toplevel            = top_generic
-xst_opts            = -vlgincdir rtl
-#ngdbuild_opts      =
-#map_opts           =
-#par_opts           =
-#netgen_opts        =
-#bitgen_opts        =
-#trce_opts          =
-# Files
-#files_vhdl          = 
+xst_opts            = -vlgincdir rtl/util
 files_verilog       = rtl/toplevel/top_generic.v
                       rtl/core/nco_q15.v
                       rtl/core/sigmadelta_sampler.v
+                      rtl/core/sigmadelta_rcmodel_q15.v
+                      rtl/core/mul_const.v
                       rtl/arch/spartan-6/lvds_comparator.v
+                      rtl/arch/spartan-6/clk_gen.v
 files_con           = boards/mimas_v1/constraints.ucf
 files_other         = rtl/util/conv.vh
+                      rtl/util/rc_alpha_q15.vh
+
+[target.ip]
+toolchain           = ISE_IP
+family              = spartan6
+device              = xc6slx9
+package             = tqg144
+speedgrade          = -2
+files_xco           = boards/mimas_v1/ip/clk_gen.xco
+
 
 [target.sim]
 toolchain           = iverilog
 runtime             = all
 toplevel            = tb_nco_q15
-ivl_opts            = -Irtl
-#vvp_opts            =
-# Files
-#files_sysverilog    = 
+ivl_opts            = -Irtl/util
 files_verilog       = sim/tb/tb_nco_q15.v
                       rtl/core/nco_q15.v
                       rtl/core/lvds_comparator.v
+                      rtl/core/sigmadelta_rcmodel_q15.v
+                      rtl/core/mul_const.v
                       sim/overrides/sigmadelta_sampler.v
-files_other         = rtl/util/conv.vh
+                      sim/overrides/clk_gen.v
+files_other         = rtl/util/conv.vh
+                      rtl/util/rc_alpha_q15.vh