Added PLL/clock generator and SD RC model

2025-10-19 15:36:55 +02:00
parent 3b04f3a6be
commit eb7caaf2c5
10 changed files with 615 additions and 16 deletions
--- a/boards/mimas_v1/constraints.ucf
+++ b/boards/mimas_v1/constraints.ucf
@@ -2,6 +2,9 @@
 NET "aclk" LOC = P126;
 NET "aclk" TNM_NET = "SYS_CLK_PIN";
 TIMESPEC TS_SYS_CLK_PIN = PERIOD "SYS_CLK_PIN" 10 ns HIGH 50 %;
+# Generated clocks
+NET "clk_15" TNM_NET = "SYS_CLK_15";
+TIMESPEC TS_SYS_CLK_15 = PERIOD "SYS_CLK_15" 13.334 ns HIGH 50%;

 # Boards button row
 NET "aresetn" LOC = P120;