joppe/fpga_modem
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Added sampler and RC model

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Jojojoppe
2025-10-01 21:15:20 +02:00
parent ee58fccba4
commit e0151d093f
17 changed files with 319 additions and 13 deletions
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modem.gprj
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@@ -5,7 +5,9 @@
<Version>5</Version>
<Device name="GW1NSR-4C" pn="GW1NSR-LV4CQN48PC7/I6">gw1nsr4c-009</Device>
<FileList>
<File path="HW/sigmadelta_sampler.v" type="file.verilog" enable="1"/>
<File path="HW/toplevel.v" type="file.verilog" enable="1"/>
<File path="IP/gw_clkdiv8/gw_clkdiv8.v" type="file.verilog" enable="1"/>
<File path="IP/gw_pllvr/gw_pllvr.v" type="file.verilog" enable="1"/>
<File path="CON/io.cst" type="file.cst" enable="1"/>
<File path="CON/timing.sdc" type="file.sdc" enable="1"/>