Added sampler and RC model

SIM/sampling_tb.v

@@ -0,0 +1,27 @@
+`timescale 1ns/1ps
+
+module sampling_tb;
+    reg clk;
+    reg reset_n;
+
+    sampling m_sampling(
+        .clk(clk),
+        .reset_n(reset_n)
+    );
+
+    initial begin
+        $dumpfile("sampling_tb.vcd");
+        $dumpvars (0, sampling_tb);
+
+        clk <= 1'b0;
+        reset_n <= 1'b0;
+        #50 reset_n <= 1'b1;
+
+        #1000000
+        $finish;
+    end
+
+    //15 MHz clock
+    always #33.33 clk = ~clk;
+
+endmodule