Added sampler and RC model

2025-10-01 21:15:20 +02:00
parent ee58fccba4
commit e0151d093f
17 changed files with 319 additions and 13 deletions
--- a/CON/timing.sdc
+++ b/CON/timing.sdc
@@ -5,3 +5,4 @@
 //Created Time: 2025-10-01 16:50:37
 create_clock -name CLK_IN -period 37.037 -waveform {0 18.518} [get_ports {clk}]
 create_clock -name CLK_120 -period 8.333 -waveform {0 4.167} [get_nets {clk_120}]
+create_clock -name CLK_15 -period 66.666 -waveform {0 33.333} [get_nets {clk_15}]