joppe/fpga_modem
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Added sampler and RC model

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Jojojoppe
2025-10-01 21:15:20 +02:00
parent ee58fccba4
commit e0151d093f
17 changed files with 319 additions and 13 deletions
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10
CON/io.cst
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@@ -4,13 +4,17 @@
//Tool Version: V1.9.12
//Part Number: GW1NSR-LV4CQN48PC7/I6
//Device: GW1NSR-4C
//Created Time: Wed 10 01 13:41:57 2025
//Created Time: Wed 10 01 18:02:30 2025
IO_LOC "adc1_A" 39,40;
IO_PORT "adc1_A" IO_TYPE=LVDS25 PULL_MODE=NONE BANK_VCCIO=3.3;
IO_LOC "adc1_O" 41;
IO_PORT "adc1_O" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "led" 10;
IO_PORT "led" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "button" 14;
IO_PORT "button" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "reset_n" 15;
IO_PORT "reset_n" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "clk" 45;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "button" 14;
IO_PORT "button" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;

1
CON/timing.sdc
View File

@@ -5,3 +5,4 @@
//Created Time: 2025-10-01 16:50:37
create_clock -name CLK_IN -period 37.037 -waveform {0 18.518} [get_ports {clk}]
create_clock -name CLK_120 -period 8.333 -waveform {0 4.167} [get_nets {clk_120}]
create_clock -name CLK_15 -period 66.666 -waveform {0 33.333} [get_nets {clk_15}]