Moved serv to own tree

project.cfg

@@ -12,7 +12,7 @@ pubkey              = /home/joppe/.ssh/id_rsa.pub
 
 [target.synth]
 toolchain           = ISE
-ise_settings        = /opt/packages/xilinx/14.7/ISE_DS/settings64.sh
+ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
 # Toolchain settings
 family              = spartan6
 device              = xc6slx9
@@ -36,36 +36,44 @@ files_con           = boards/mimas_v1/constraints.ucf
 files_other         = rtl/util/conv.vh
 
 [target.serv]
-toolchain           = iverilog
-runtime             = all
-toplevel            = tb_serving
-ivl_opts            = -Irtl
-files_verilog       = external/serv/rtl/serv_aligner.v
-                      external/serv/rtl/serv_alu.v
-                      external/serv/rtl/serv_bufreg.v
-                      external/serv/rtl/serv_bufreg2.v
-                      external/serv/rtl/serv_compdec.v
-                      external/serv/rtl/serv_csr.v
-                      external/serv/rtl/serv_ctrl.v
-                      external/serv/rtl/serv_debug.v
-                      external/serv/rtl/serv_decode.v
-                      external/serv/rtl/serv_immdec.v
-                      external/serv/rtl/serv_mem_if.v
-                      external/serv/rtl/serv_rf_if.v
-                      external/serv/rtl/serv_rf_ram_if.v
-                      external/serv/rtl/serv_rf_ram.v
-                      external/serv/rtl/serv_rf_top.v
-                      external/serv/rtl/serv_state.v
-                      external/serv/rtl/serv_synth_wrapper.v
-                      external/serv/rtl/serv_top.v
-                      external/serv/servile/servile_arbiter.v
-                      external/serv/servile/servile_mux.v
-                      external/serv/servile/servile_rf_mem_if.v
-                      external/serv/servile/servile.v
-                    #   external/serv/serving/serving_ram.v
-                      sim/overrides/serving_ram.v
-                      external/serv/serving/serving.v
-                      sim/tb/tb_serving.v
+toolchain           = ISE
+ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
+family              = spartan6
+device              = xc6slx9
+package             = tqg144
+speedgrade          = -2
+toplevel            = top_generic
+xst_opts            = -vlgincdir rtl
+files_con           = boards/mimas_v1/constraints.ucf
+files_other         = sw/blinky/blinky.hex
+files_verilog       = rtl/util/clog2.vh
+                      rtl/serv/serv_aligner.v
+                      rtl/serv/serv_alu.v
+                      rtl/serv/serv_bufreg.v
+                      rtl/serv/serv_bufreg2.v
+                      rtl/serv/serv_compdec.v
+                      rtl/serv/serv_csr.v
+                      rtl/serv/serv_ctrl.v
+                      rtl/serv/serv_debug.v
+                      rtl/serv/serv_decode.v
+                      rtl/serv/serv_immdec.v
+                      rtl/serv/serv_mem_if.v
+                      rtl/serv/serv_rf_if.v
+                      rtl/serv/serv_rf_ram_if.v
+                      rtl/serv/serv_rf_ram.v
+                      rtl/serv/serv_rf_top.v
+                      rtl/serv/serv_state.v
+                      rtl/serv/serv_synth_wrapper.v
+                      rtl/serv/serv_top.v
+                      rtl/serv/servile_arbiter.v
+                      rtl/serv/servile_mux.v
+                      rtl/serv/servile_rf_mem_if.v
+                      rtl/serv/servile.v
+                      rtl/serv/serving_ram.v
+                      # sim/overrides/serving_ram.v
+                      rtl/serv/serving.v
+                      rtl/wb/wb_gpio.v
+                      rtl/toplevel/top_serv.v
 
 [target.sim]
 toolchain           = iverilog