Added some stuff from modem and added formal

cores/wb/wb_gpio/formal/formal_wb_gpio.v

@@ -0,0 +1,69 @@
+`timescale 1ns/1ps
+
+module formal_wb_gpio #(
+    parameter [31:0] address = 32'h00000000
+);
+    (* gclk *) reg        i_wb_clk;
+    (* anyseq *) reg      i_rst;
+    (* anyseq *) reg      i_wb_rst;
+    (* anyseq *) reg [31:0] i_wb_adr;
+    (* anyseq *) reg [31:0] i_wb_dat;
+    (* anyseq *) reg [3:0]  i_wb_sel;
+    (* anyseq *) reg      i_wb_we;
+    (* anyseq *) reg      i_wb_stb;
+    (* anyseq *) reg [31:0] i_gpio;
+    wire [31:0] o_wb_rdt;
+    wire        o_wb_ack;
+    wire [31:0] o_gpio;
+    wire        i_wb_cyc;
+    reg         f_past_valid;
+
+    assign i_wb_cyc = i_wb_stb || o_wb_ack;
+
+    wb_gpio #(
+        .address(address)
+    ) dut (
+        .i_wb_clk(i_wb_clk),
+        .i_wb_rst(i_wb_rst),
+        .i_wb_adr(i_wb_adr),
+        .i_wb_dat(i_wb_dat),
+        .i_wb_sel(i_wb_sel),
+        .i_wb_we(i_wb_we),
+        .i_wb_stb(i_wb_stb),
+        .i_gpio(i_gpio),
+        .o_wb_rdt(o_wb_rdt),
+        .o_wb_ack(o_wb_ack),
+        .o_gpio(o_gpio)
+    );
+
+    formal_wb_slave_checker wb_checker (
+        .i_clk(i_wb_clk),
+        .i_rst(i_rst),
+        .i_wb_rst(i_wb_rst),
+        .i_wb_adr(i_wb_adr),
+        .i_wb_dat(i_wb_dat),
+        .i_wb_sel(i_wb_sel),
+        .i_wb_we(i_wb_we),
+        .i_wb_stb(i_wb_stb),
+        .i_wb_cyc(i_wb_cyc),
+        .o_wb_rdt(o_wb_rdt),
+        .o_wb_ack(o_wb_ack)
+    );
+
+    initial f_past_valid = 1'b0;
+
+    always @(posedge i_wb_clk) begin
+        f_past_valid <= 1'b1;
+
+        // R1: reads return the sampled GPIO input on the following cycle
+        if (f_past_valid && !$past(i_wb_rst) && !i_wb_rst && $past(i_wb_stb) && !$past(i_wb_we)) begin
+            assert(o_wb_rdt == $past(i_gpio));
+        end
+
+        // R2: reset clears the output register and read data register
+        if (f_past_valid && $past(i_wb_rst)) begin
+            assert(o_gpio == 32'h00000000);
+            assert(o_wb_rdt == 32'h00000000);
+        end
+    end
+endmodule

cores/wb/wb_gpio/formal/wb_gpio.sby

@@ -0,0 +1,13 @@
+[options]
+mode prove
+depth 8
+
+[engines]
+smtbmc z3 parallel.enable=true parallel.threads.max=8
+
+[script]
+{{"-formal"|gen_reads}}
+prep -top {{top_level}}
+
+[files]
+{{files}}

cores/wb/wb_gpio/formal/wb_gpio/config.sby

@@ -0,0 +1,13 @@
+[options]
+mode prove
+depth 8
+
+[engines]
+smtbmc z3 parallel.enable=true parallel.threads.max=8
+
+[script]
+{{"-formal"|gen_reads}}
+prep -top {{top_level}}
+
+[files]
+{{files}}

cores/wb/wb_gpio/formal/wb_gpio/logfile.txt

@@ -0,0 +1,2 @@
+SBY 17:32:33 [cores/wb/wb_gpio/formal/wb_gpio] Removing directory '/data/joppe/projects/fusesoc_test/cores/wb/wb_gpio/formal/wb_gpio'.
+SBY 17:32:33 [cores/wb/wb_gpio/formal/wb_gpio] Copy '/data/joppe/projects/fusesoc_test/{{files}}' to '/data/joppe/projects/fusesoc_test/cores/wb/wb_gpio/formal/wb_gpio/src/{{files}}'.

cores/wb/wb_gpio/rtl/wb_gpio.v

@@ -0,0 +1,56 @@
+module wb_gpio #(
+  parameter address = 32'h00000000
+)(
+  input  wire        i_wb_clk,
+  input  wire        i_wb_rst,   // optional; tie low if unused
+  input  wire [31:0] i_wb_adr,   // optional; can ignore for single-reg
+  input  wire [31:0] i_wb_dat,
+  input  wire [3:0]  i_wb_sel,
+  input  wire        i_wb_we,
+  input  wire        i_wb_stb,
+  input  wire [31:0] i_gpio,
+
+  output reg  [31:0] o_wb_rdt,
+  output reg         o_wb_ack,
+  output reg  [31:0] o_gpio
+);
+
+  initial o_gpio <= 32'h00000000;
+  initial o_wb_rdt <= 32'h00000000;
+
+  wire addr_check;
+  assign addr_check = (i_wb_adr == address);
+
+  // One-cycle ACK pulse per request (works even if stb stays high)
+  initial o_wb_ack <= 1'b0;
+  always @(posedge i_wb_clk) begin
+    if (i_wb_rst) begin
+      o_wb_ack <= 1'b0;
+    end else begin
+      o_wb_ack <= i_wb_stb & ~o_wb_ack; // pulse while stb asserted
+    end
+  end
+
+  // Read data (combinational or registered; registered here)
+  always @(posedge i_wb_clk) begin
+    if (i_wb_rst) begin
+      o_wb_rdt <= 32'h0;
+    end else if (i_wb_stb && !i_wb_we) begin
+      o_wb_rdt <= i_gpio;
+    end
+  end
+
+  // Write latch (update on the acknowledged cycle)
+  always @(posedge i_wb_clk) begin
+    if (i_wb_rst) begin
+      o_gpio <= 32'h0;
+    end else if (i_wb_stb && i_wb_we && addr_check && (i_wb_stb & ~o_wb_ack)) begin
+      // Apply byte enables (so sb works if the master uses sel)
+      if (i_wb_sel[0]) o_gpio[7:0]   <= i_wb_dat[7:0];
+      if (i_wb_sel[1]) o_gpio[15:8]  <= i_wb_dat[15:8];
+      if (i_wb_sel[2]) o_gpio[23:16] <= i_wb_dat[23:16];
+      if (i_wb_sel[3]) o_gpio[31:24] <= i_wb_dat[31:24];
+    end
+  end
+
+endmodule

cores/wb/wb_gpio/wb_gpio.core

@@ -0,0 +1,43 @@
+CAPI=2:
+
+name: joppeb:wb:wb_gpio:1.0
+description: Wishbone GPIO peripheral
+
+filesets:
+    rtl:
+        files:
+            - rtl/wb_gpio.v
+        file_type: verilogSource
+    formal_rtl:
+        depend:
+            - joppeb:wb:formal_checker
+        files:
+            - formal/formal_wb_gpio.v
+        file_type: verilogSource
+    formal_cfg:
+        files:
+            - formal/wb_gpio.sby
+        file_type: sbyConfigTemplate
+
+targets:
+    default:
+        filesets:
+            - rtl
+        toplevel: wb_gpio
+        parameters:
+            - address
+    formal:
+        default_tool: symbiyosys
+        filesets:
+            - rtl
+            - formal_rtl
+            - formal_cfg
+        toplevel: formal_wb_gpio
+        parameters:
+            - address
+
+parameters:
+    address:
+        datatype: int
+        description: Wishbone address matched by this peripheral
+        paramtype: vlogparam