Added some stuff from modem and added formal

2026-02-28 18:23:39 +01:00
parent fa641b1eab
commit cf7e03b9fe
55 changed files with 3717 additions and 31 deletions
--- a/cores/util/clog2/clog2.core
+++ b/cores/util/clog2/clog2.core
@@ -0,0 +1,16 @@
+CAPI=2:
+
+name: joppeb:util:clog2:1.0
+description: Verilog-2001 compatible ceil(log2(x)) macro header
+
+filesets:
+    include:
+        files:
+            - clog2.vh:
+                is_include_file: true
+        file_type: verilogSource
+
+targets:
+    default:
+        filesets:
+            - include