Added some stuff from modem and added formal

cores/signal/nco_q15/tb/tb_nco_q15.v

@@ -0,0 +1,42 @@
+`timescale 1ns/1ps
+
+module tb_nco_q15();
+    // Clock and reset generation
+    reg clk;
+    reg resetn;
+    initial clk <= 1'b0;
+    initial resetn <= 1'b0;
+    always #4.17 clk <= !clk;
+    initial #40 resetn <= 1'b1;
+
+    reg [31:0] freq;
+    wire [15:0] sin_q15;
+    wire [15:0] cos_q15;
+    wire out_en;
+
+    nco_q15 #(.CLK_HZ(120_000_000), .FS_HZ(40_000)) nco (
+        .clk    (clk),
+        .rst_n  (resetn),
+        .freq_hz(freq),
+        .sin_q15(sin_q15),
+        .cos_q15(cos_q15),
+        .clk_en (out_en)
+    );
+
+    initial begin
+        $dumpfile("out.vcd");
+        $dumpvars;
+
+        freq = 32'h0;
+        #100
+        freq = 32'd1000;
+        #2_500_000
+        freq = 32'd2000;
+        #2_500_000
+        freq = 32'd600;
+        #2_500_000
+
+        $finish;
+    end;
+
+endmodule