Added some stuff from modem and added formal

2026-02-28 18:23:39 +01:00
parent fa641b1eab
commit cf7e03b9fe
55 changed files with 3717 additions and 31 deletions
--- a/cores/primitive/clkgen/clkgen.core
+++ b/cores/primitive/clkgen/clkgen.core
@@ -0,0 +1,49 @@
+CAPI=2:
+
+name: joppeb:primitive:clkgen:1.0
+description: Parameterized clock generator wrapper
+
+filesets:
+    wrapper:
+        files:
+            - clkgen.v
+        file_type: verilogSource
+    generic:
+        files:
+            - clkgen_generic_impl.v
+        file_type: verilogSource
+    spartan6:
+        files:
+            - clkgen_spartan6.v
+        file_type: verilogSource
+
+targets:
+    default:
+        filesets:
+            - wrapper
+            - generic
+            - spartan6
+        toplevel: clkgen
+        parameters:
+            - CLK_IN_HZ
+            - CLKFX_DIVIDE
+            - CLKFX_MULTIPLY
+            - CLKDV_DIVIDE
+
+parameters:
+    CLK_IN_HZ:
+        datatype: int
+        description: Input clock frequency in Hz
+        paramtype: vlogparam
+    CLKFX_DIVIDE:
+        datatype: int
+        description: DCM CLKFX divide value
+        paramtype: vlogparam
+    CLKFX_MULTIPLY:
+        datatype: int
+        description: DCM CLKFX multiply value
+        paramtype: vlogparam
+    CLKDV_DIVIDE:
+        datatype: real
+        description: DCM CLKDV divide value
+        paramtype: vlogparam